In manufacturing semiconductors, it is required to form a fine wiring pattern along with a trend toward miniaturization of semiconductor devices. For example, Japanese Patent Application Publication No. H11-354505 discloses a technique related to a method for manufacturing a dielectric thin film device for improving microprocessing accuracy. Japanese Patent Application No. 2016-121820 discloses a technique for performing selective pattern formation while suppressing complication of processing.
In the case of forming a fine wiring pattern, there is known a technique for performing etching in a vertical direction while suppressing etching of a side surface by forming a carbon-based etching target film on the side surface by using, e.g., CxFy-based gas or the like. In that case, a sufficient difference in an etching rate between layers may be required to maintain a pattern shape during a plurality of etching processes. However, in the case of forming layers requring different etching rates along a pre-difined fine wiring pattern, complicated processes may be required. Therefore, there is required a technique of, while maintaining a shape of a pattern, easily laminating a layer having a shape corresponding to the pattern shape on the pattern.